Thyristor Semiconductor Products Page 25 Thyristor

2014 Littelfuse, Inc. Specifications are subject to change without notice. Revised: 12/14/14 Teccor brand Thyristors AN1002 Latching Current of SCRs and Triacs MT2 POSITIVE (Positive Half Cycle) MT2 NEGATIVE (Negative Half Cycle) MT1 MT2 + I GT REF QII MT1 I GT GATE MT2 REF MT1 MT2 REF MT1 MT2 REF QI QIV QIII ALL POLARITIES ARE REFERENCED TO MT1 (-) I GT GATE (+) I GT - I GT GATE (-) I GT GATE (+) + - NOTE: Alternistors will not operate in Q IV 2.0 1.5 1.0 .5 0 -40 -15 +25 +65 +100 Case Temperature (T C ) - C Ratio of I GT I GT (T C = 25C) Gate Pulse (Gate Drive to Thyristor) Principal Current Through Thyristor Latching Current Requirement Time Zero Crossing Point Time Figure AN1002.5 Latching Characteristic of Thyristor (Device Not Latched) Figure AN1002.4 Typical DC Gate Trigger Current versus Case Temperature For applications where low temperatures are expected, gate current supply should be increased to at least two to eight times the gate trigger current requirements at 25 C. The actual factor varies by Thyristor type and the environmental temperature. Figure AN1002.3 Definition of Operating Quadrants in Triacs Triacs can be gated on in one of four basic gating modes as shown in Figure AN1002.3. The most common quadrants for gating on Triacs are Quadrants I and III, where the gate supply is synchronized with the main terminal supply (gate positive -- MT2 positive, gate negative -- MT2 negative). Optimum Triac gate sensitivity is achieved when operating in Quadrants I and III due to the inherent Thyristor chip construction. If Quadrants I and III cannot be used, the next best operating modes are Quadrants II and III where the gate supply has a negative polarity with an AC main terminal supply. Typically, Quadrant II is approximately equal in gate sensitivity to Quadrant I; however, latching current sensitivity in Quadrant II is lowest. Therefore, it is difficult for Triacs to latch on in Quadrant II when the main terminal current supply is very low in value. Special consideration should be given to gating circuit design when Quadrants I and IV are used in actual application, because Quadrant IV has the lowest gate sensitivity of all four operating quadrants. The following table shows the relationships between different gating modes in current required to gate on Triacs. I GT (in given Quadrant) Typical Ratio of ------------------------------------------ at 25 O C I GT (Quadrant 1) Type Operating Mode Quadrant I Quadrant II Quadrant III Quadrant IV 4 A Triac 1 1.6 2.5 2.7 10 A Triac 1 1.5 1.4 3.1 Example of 4 A Triac: If I GT (I) = 10 mA, then I GT (II) = 16 mA I GT (III) = 25 mA I GT (IV) = 27 mA Gate trigger current is temperature-dependent as shown in Figure AN1002.4. Thyristors become less sensitive with decreasing temperature and more sensitive with increasing temperature. If I GT (I) = 10 mA at 25 C, then I GT (I) = 20 mA at -40 C In applications where high di/dt, high surge, and fast turn-on are expected, gate drive current should be steep rising (1 s rise time) and at least twice rated I GT or higher current magnitude is very high, then duration may have to be limited to keep from overstressing (exceeding the power dissipation limit of) gate junction. Latching current (I L ) is the minimum principal current required to maintain the Thyristor in the on state immediately after the switching from off state to on state has occurred and the triggering signal has been removed. Latching current can best be understood by relating to the AN1002.5 and Figure AN1002.6 illustrate typical Thyristor latching phenomenon. In the illustrations in Figure AN1002.5, the Thyristor does not stay on after gate drive is removed due to insufficient available principal current (which is lower than the latching current requirement). In the illustration in Figure AN1002.6 the device stays on for the remainder of the half cycle until the principal current falls below the holding current level. Figure AN1002.5 shows the characteristics of the same device if gate drive is removed or shortened before latching current requirement has been met. Gating, Latching, and Holding of SCRs and Triacs (continued)

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