Sidactor Protection Thyristor Products Page 22 SIDACtor Protection Thyristor Products

SIDACtor Protection Thyristors 2017 Littelfuse, Inc. Specifications are subject to change without notice. Revised: 02/23/17 PCB Layout Considerations for an Ethernet Application or Other High Speed Circuits 1. Use at least a 4-layer PCB (this stack-up allows routing of critical signal traces without vias). 2. 2nd layer is a solid and contiguous ground plane. 3. 3rd layer is a solid power plane. 4. 4th layer is for bottom signal traces. 5. Use a single ground plane connection to chassis ground (reduces EMI and improves ESD resistibility characteristics). 6. Use void areas on both ground and power plane under any magnetic. 7. No PCB traces with 90 turns and proper width as indicated in SIDACtor catalogue. 8. Avoid vias and pads for any critical signals. 9. Use controlled impedances on all high speed traces with correct terminations (all differential signal traces should be equal length). a) 5-mil trace width and 5-mil trace separation of identical length and short as possible for TX/RX signal lines with 100 ohm controlled trace impedance pair (i.e. 50 ohm single-ended). b) If possible, separate adjacent TX/RX pairs > 20 mils apart from each other to reduce crosstalk issues. 10. Recognize propagation delays for traces on an outer layer is approximately 145 pS/inch while embedded trace between planes is approximately 180 pS/inch. a) Circuit board traces are generally considered as transmission lines if the unloaded signal transition (rise/ fall) time is round-trip propagation delay on the trace. b) When this condition exists (PCB traces = transmission line) then line impedance control (exact and constant) is utmost importance. c) Use an in-line TVS Diode Array or SEP SIDACtor overvoltage protection device that allows traces to go directly underneath the device rather than using stub connections is best (minimizes signal ringing and signal reflections). 11. FR-4 PCB material is good for frequencies up to 500 MHz (but GE-Tek materials could be considered for performance enhancement over FR-4). 12. Place all IC coupling capacitors as close as practicable to IC with minimized lead lengths or SMT (same guidance for all crystal components). 13. Implement at least 0.30 inches separation between all PCB layers and PCB chassis ground. 14. Use a 1nF 2 kV capacitor between power supply ground and chassis ground. 15. Place high speed devices in close proximity to power supply so that shortest trace lengths can be used (reduces ground bounce). 16. Place overvoltage and overcurrent protection and transformer as close as possible to RJ45 connector. 17. For CAT5e systems, consider using 52 in Bob Smith termination circuit instead of 75 . 18. For CAT6 systems, consider using 66 resistor in Bob Smith termination circuit instead of 75 .

Previous Page
Next Page