Esd Suppression Design Guide Page 4 ESD Suppression Design Guide

Figure 1. ESD Test Waveform 100 90 % Current (I) % tr = 0.7 to 1.0ns 30ns 60ns I 60 I 30 ESD Suppression and Circuit Design Considerations Proper use of ESD circuit protection helps prevent these failures. Still, selection of a suppression device must recognize that ESD has very short rise and fall times- less than one nanosecond (1ns) in most cases. The International Electrotechnical Commission (IEC) has developed a specification (IEC 61000-4-2) for ESD testing that helps determine if products are susceptible to ESD events. Littelfuse device engineers use specifications like these to design ESD suppressors with the speed, clamping voltage, and residual current levels that will protect today's sensitive semiconductors and electronic circuitry. Many of these designs have the low internal capacitance needed for high bandwidth communications. When selecting ESD suppressors, circuit designers need to consider potential coupling paths that would allow ESD to enter their equipment and circuits. These weak points identify areas that should be considered for ESD suppressor installation. Ultimately, designers need to select ESD suppressors with characteristics appropriate for their type of equipment, the component sensitivity, and the environment where it will be used. A robust web-based tool to help circuit designers identify the optimal electronic fuses for their products. Littelfuse iDesign TM Online Fuse Design and Selection Tool 2016 Littelfuse ESD Suppression Design Guide ESD Suppresion Design Guide ESD Damage, Suppression Requirements and Considerations ESD Damage ESD is characterized by fast rise times and high peak voltages and currents up to 30 amps (per IEC 61000- 4-2, level 4), which can melt silicon and conductor traces. However, ESD effects can be more subtle. The three types of damage are: 1. Soft Failures Electrical currents due to ESD can change the state of internal logic, causing a system to latch up or behave unpredictably, or cause corruption of a data stream. While this is temporary, it may slow down communications, or require a system reboot in the case of lockup. 2. Latent Defects A component or circuit may be damaged by ESD and its function degraded though the system will continue to work. However, this type of defect often progresses to a premature failure. 3. Catastrophic Failures Of course, ESD can damage a component to the point where it does not function as intended, or doesn't work at all. ESD Suppression Requirements The likelihood of electronic circuit damage is increasing as integrated circuit (IC) dimensions are shrinking to nano- meter sizes. Most ICs operate at low voltages and have structures and conductive paths that cannot survive the high currents and voltages associated with ESD transients. Another significant trend is the migration to higher fre- quency communication devices to transmit more informa- tion in less time. This means that ESD solutions must not compromise stringent signal integrity requirements at the higher data rates. Therefore, ESD suppressors must have low internal capacitance so that data communication signals are not distorted. IC designers add a limited amount of ESD suppression to their chips to help avoid damage during manufacturing and assembly processes. However, the level of protec- tion that is added may not be sufficient to protect ICs and other semiconductor devices from ESD during actual usage. Many electronic products, especially portable ones, are used in uncontrolled environments. Portable devices can experience a charge buildup as they are carried by users on their person or in a purse. This energy can then be discharged to another device as the two are connected, usually when a user touches I/O pins on a cable connec- tor. Therefore, end product designers should consider adding ESD suppressors to their circuits. 3

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